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general description the max8732a/max8733a/max8734a dual step-down, switch-mode power-supply (smps) controllers generate logic-supply voltages in battery-powered systems. the max8732a/max8733a/max8734a include two pulse- width modulation (pwm) controllers, adjustable from 2v to 5.5v or fixed at 5v and 3.3v. these devices feature two linear regulators providing 5v and 3.3v always-on out- puts. each linear regulator provides up to 100ma output current with automatic linear-regulator bootstrapping to the main smps outputs. the max8732a/max8733a/ max8734a include on-board power-up sequencing, a power-good (pgood) output, digital soft-start, and inter- nal soft-stop output discharge that prevents negative volt- ages on shutdown. additionally, the outputs are high impedance when v cc falls below its uvlo set point while the outputs are enabled. maxim? proprietary quick-pwm quick-response, con- stant on-time pwm control scheme operates without sense resistors and provides 100ns response to load tran- sients while maintaining a relatively constant switching fre- quency. the unique ultrasonic pulse-skipping mode maintains the switching frequency above 25khz, which eliminates noise in audio applications. other features include pulse skipping, which maximizes efficiency in light-load applications, and fixed-frequency pwm mode, which reduces rf interference in sensitive applications. the max8732a features a 200khz/5v and 300khz/3.3v smps for highest efficiency, while the max8733a fea- tures a 400khz/5v and 500khz/3.3v smps for ?hin and light?applications. the max8734a provides a pin- selectable switching frequency, allowing either 200khz/ 300khz or 400khz/500khz operation of the 5v/3.3v smpss, respectively. the max8732a/max8733a/ max8734a are available in 28-pin qsop packages and operate over the extended temperature range (-40? to +85?). the max8732a/max8733a/max8734a are pin-for-pin upgrades to the max1777/max1977/max1999. the max1999 evaluation kit (ev kit) can be used to evaluate the max8732a/max8733a/max8734a. applications notebook and subnotebook computers pdas and mobile communication devices 3- and 4-cell li+ battery-powered devices features ? no current-sense resistor needed (max8734a) ? accurate current sense with current-sense resistor (max8732a/max8733a) ? 1.5% output voltage accuracy ? 3.3v and 5v 100ma bootstrapped linear regulators ? internal soft-start and soft-stop output discharge ? quick-pwm with 100ns load step response ? 3.3v and 5v fixed or adjustable outputs (dual mode) ? 4.5v to 24v input voltage range ? enhanced ultrasonic pulse-skipping mode (25khz min) ? power-good (pgood) signal ? overvoltage protection enable/disable max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ________________________________________________________________ maxim integrated products 1 ordering information 19-3711; rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- pa cka ge 5v/3.3v switching frequency ( khz) max8732a eei+ -40? to +85? 28 qsop 200/300 max8732aeei -40? to +85? 28 qsop 200/300 max8733a eei+ -40? to +85? 28 qsop 400/500 max8733aeei -40? to +85? 28 qsop 400/500 quick-pwm and dual mode are trademarks of maxim integrated products, inc. ordering information continued at end of data sheet. + denotes lead-free package. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bst3 lx3 dh3 ldo3 dl3 gnd lx5 out3 out5 v+ dl5 ldo5 v cc dh5 bst5 ton ilim5 fb5 ref fb3 ilim3 on5 on3 pgood n.c. qsop top view max8734a shdn pro skip pin configurations pin configurations continued at end of data sheet.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , v shdn = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+, shdn to gnd ..................................................-0.3v to +25v bst_ to gnd ..........................................................-0.3v to +30v lx_ to bst_ ..............................................................-6v to +0.3v cs_ to gnd (max8732a/max8733a only) .................-2v to +6v v cc , ldo5, ldo3, out3, out5, on3, on5, ref, fb3, fb5, skip , pro , pgood to gnd ...............-0.3v to +6v dh3 to lx3 ..............................................-0.3v to (v bst3 + 0.3v) dh5 to lx5 ..............................................-0.3v to (v bst5 + 0.3v) ilim3, ilim5 to gnd...................................-0.3v to (v cc + 0.3v) dl3, dl5 to gnd....................................-0.3v to (v ldo5 + 0.3v) ton to gnd (max8734a only) ................................-0.3v to +6v ldo3, ldo5, ref short circuit to gnd ....................momentary ldo3 current (internal regulator) continuous................+100ma ldo3 current (switched over to out3) continuous ......+200ma ldo5 current (internal regulator) continuous................+100ma ldo5 current (switched over to out5) continuous ......+200ma continuous power dissipation (t a = +70?) 28-pin qsop (derate 10.8mw/? above +70?).........860mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units main smps controllers ldo5 in regulation 6 24 v+ input voltage range v+ = ldo5, v out5 < 4.43v 4.5 5.5 v 3.3v output voltage in fixed mode v+ = 6v to 24v, fb3 = gnd, v skip = 5v 3.285 3.330 3.375 v v+ = 6v to 24v, fb5 = gnd, v skip = 5v, max8732a/max8734a (ton = v cc ) 5v output voltage in fixed mode v+ = 7v to 24v, fb5 = gnd, v skip = 5v, max8733a/max8734a (ton = gnd) 4.975 5.050 5.125 v output voltage in adjustable mode v+ = 6v to 24v, either smps 1.975 2.00 2.025 v output voltage adjust range either smps 2.0 5.5 v fb3, fb5 adjustable-mode threshold voltage dual-mode comparator 0.1 0.2 v either smps, v skip = 5v, 0 to 5a -0.1 either smps, skip = gnd, 0 to 5a -1.5 dc load regulation either smps, v skip = 2v, 0 to 5a -1.7 % line regulation either smps, 6v < v+ < 24v 0.005 %/v current-limit threshold (positive, default) ilim_ = v cc , gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) 93 100 107 mv v ilim_ = 0.5v 40 50 60 v ilim_ = 1v 93 100 107 current-limit threshold (positive, adjustable) gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) v ilim_ = 2v 185 200 215 mv zero-current threshold skip = gnd, ilim_ = v cc , gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) 3mv current-limit threshold (negative, default) skip = ilim_ = v cc , gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) -120 mv soft-start ramp time zero to full limit 1.7 ms
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , v shdn = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units 5v smps 200 max8732a or max8734a (v ton = 5v), skip = v cc 3.3v smps 300 5v smps 400 max8733a or max8734a (v ton = 0), skip = v cc 3.3v smps 500 operating frequency skip = ref 25 36 khz v out5 = 5.05v 1.895 2.105 2.315 max8732a or max8734a (v ton = 5v) v out3 = 3.33v 0.833 0.925 1.017 v out5 = 5.05v 0.895 1.052 1.209 on-time pulse width max8733a or max8734a (v ton = 0) v out3 = 3.33v 0.475 0.555 0.635 ? minimum off-time 250 300 350 ns v out5 = 5.05v 94 max8732a or max8734a (v ton = 5v) v out3 = 3.33v 91 v out5 = 5.05v 88 maximum duty cycle max8733a or max8734a (v ton = 0) v out3 = 3.33v 85 % internal regulator and reference ldo5 output voltage on3 = on5 = gnd, 6v < v+ < 24v, 0 < i ldo5 < 100ma 4.90 5.00 5.10 v ldo5 short-circuit current ldo5 = gnd 190 ma ldo5 undervoltage-lockout fault threshold falling edge of ldo5, hysteresis = 1% 3.7 4.0 4.3 v ldo5 bootstrap switch threshold falling edge of out5, rising edge at out5 regulation point 4.43 4.56 4.69 v ldo5 bootstrap switch resistance ldo5 to out5, v out5 = 5v 1.4 3.2 ? ldo3 output voltage on3 = on5 = gnd, 6v < v+ < 24v, 0 < i ldo3 < 100ma 3.28 3.35 3.42 v ldo3 short-circuit current ldo3 = gnd 180 ma ldo3 bootstrap switch threshold falling edge of out3, rising edge at out3 regulation point 2.80 2.91 3.02 v ldo3 bootstrap switch resistance ldo3 to out3, v out3 = 3.2v 1.5 3.5 ? ref output voltage no external load 1.980 2.000 2.020 v ref load regulation 0 < i load < 50? 10 mv ref sink current ref in regulation 10 ? v+ operating supply current ldo5 switched over to out5, 5v smps 25 50 ? v+ standby supply current v+ = 6v to 24v, both smpss off, includes i shdn s s p sps skip = gnd, v out3 = 3.5v, v out5 = 5.3v 3 4.5 mw fault detection overvoltage trip threshold fb3 or fb5 with respect to nominal regulation point +8 +11 +14 %
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , v shdn = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units overvoltage fault propagation delay fb3 or fb5 delay with 50mv overdrive 10 ? pgood threshold fb3 or fb5 with respect to nominal output, falling edge, typical hysteresis = 1% -12 -9.5 -7 % pgood propagation delay falling edge, 50mv overdrive 10 ? pgood output low voltage i sink = 4ma 0.3 v pgood leakage current high state, forced to 5.5v 1 a thermal-shutdown threshold +160 o c output undervoltage shutdown threshold fb3 or fb5 with respect to nominal output voltage 65 70 75 % output undervoltage shutdown blanking time from on_ signal 10 22 35 ms inputs and outputs feedback input leakage current v fb3 = v fb5 = 2.2v -200 +40 +200 na low level 0.6 pro input voltage high level 1.5 v low level 0.8 float level 1.7 2.3 skip input voltage high level 2.4 v low level 0.8 ton input voltage high level 2.4 v clear fault level/smps off level 0.8 delay start level 1.7 2.3 on3, on5 input voltage smps on level 2.4 v v pro or v ton = 0 or 5v -1 +1 v on_ = 0 or 5v -2 +2 v skip = 0 or 5v -1 +1 v shdn = 0 or 24v -1 +1 v cs_ = 0 or 5v -2 +2 input leakage current v ilim3 , v ilim5 = 0 or 2v -0.2 +0.2 ? rising edge 1.2 1.6 2.0 shdn input trip level falling edge 0.96 1.00 1.04 v dh_ gate-driver sink/source current dh3, dh5 forced to 2v 2 a dl_ gate-driver source current dl3 (source), dl5 (source), forced to 2v 1.7 a dl_ gate-driver sink current dl3 (sink), dl5 (sink), forced to 2v 3.3 a dh_ gate-driver on-resistance bst - lx_ forced to 5v 1.5 4.0 ? dl_, high state (pullup) 2.2 5.0 dl_ gate-driver on-resistance dl_, low state (pulldown) 0.6 1.5 ?
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , v shdn = 5v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units out3, out5 discharge-mode on-resistance 12 40 ? out3, out5 discharge-mode synchronous rectifier turn-on level 0.2 0.3 0.4 v electrical characteristics (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , v shdn = 5v, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter conditions min typ max units main smps controllers ldo5 in regulation 6 24 v+ input voltage range v+ = ldo5, v out5 < 4.41v 4.5 5.5 v 3.3v output voltage in fixed mode v+ = 6v to 24v, fb3 = gnd, v skip = 5v 3.27 3.39 v v+ = 6v to 24v, fb5 = gnd, v skip = 5v, max8732a/max8734a (ton = v cc ) 5v output voltage in fixed mode v+ = 7v to 24v, fb5 = gnd, v skip = 5v, max8733a/max8734a (ton = gnd) 4.95 5.15 v output voltage in adjustable mode v+ = 6v to 24v, either smps 1.97 2.03 v output voltage adjust range either smps 2.0 5.5 v fb3, fb5 adjustable-mode threshold voltage dual-mode comparator 0.1 0.2 v current-limit threshold (positive, default) ilim_ = v cc , gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) 90 110 mv v ilim_ = 0.5v 40 60 v ilim_ = 1v 90 110 current-limit threshold (positive, adjustable) gnd - cs_ (max8732a/max8733a), gnd - lx_ (max8734a) v ilim_ = 2v 180 220 mv v out5 = 5.05v 1.895 2.315 max8732a or max8734a (v ton = 5v) v out3 = 3.33v 0.833 1.017 v out5 = 5.05v 0.895 1.209 on-time pulse width max8733a or max8734a (v ton = 0) v out3 = 3.33v 0.475 0.635 ? minimum off-time 200 400 ns internal regulator and reference ldo5 output voltage on3 = on5 = gnd, 6v < v+ < 24v, 0 < i ldo5 < 100ma 4.90 5.10 v ldo5 undervoltage-lockout fault threshold falling edge of ldo5, hysteresis = 1% 3.7 4.3 v
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12.0.v, on3 = on5 = v cc , v shdn = 5v, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter conditions min typ max units ldo5 bootstrap switch threshold falling edge of out5, rising edge at out5 regulation point 4.43 4.69 v ldo5 bootstrap switch resistance ldo5 to out5, v out5 = 5v 3.2 ? ldo3 output voltage on3 = on5 = gnd, 6v < v+ < 24v, 0 < i ldo3 < 100ma 3.27 3.43 v ldo3 bootstrap switch threshold falling edge of out3, rising edge at out3 regulation point 2.80 3.02 v ldo3 bootstrap switch resistance ldo3 to out3, v out3 = 3.2v 3.5 ? ref output voltage no external load 1.975 2.025 v ref load regulation 0 < i load < 50? 10 mv ref sink current ref in regulation 10 ? v+ operating supply current ldo5 switched over to out5, 5v smps 50 ? v+ standby supply current v+ = 6v to 24v, both smpss off, includes i shdn 300 ? v+ shutdown supply current v+ = 4.5v to 24v 15 ? quiescent power consumption both smpss on, fb3 = fb5 = skip = gnd, v out3 = 3.5v, v out5 = 5.3v 4.5 mw fault detection overvoltage trip threshold fb3 or fb5 with respect to nominal regulation point +8 +14 % pgood threshold fb3 or fb5 with respect to nominal output, falling edge, typical hysteresis = 1% -12 -7 % pgood output low voltage i sink = 4ma 0.3 v pgood leakage current high state, forced to 5.5v 1 a output undervoltage shutdown threshold fb3 or fb5 with respect to nominal output voltage 65 75 % output undervoltage shutdown blanking time from on_ signal 10 40 ms inputs and outputs feedback input leakage current v fb3 = v fb5 = 2.2v -200 +200 na low level 0.6 pro input voltage high level 1.5 v low level 0.8 float level 1.7 2.3 skip input voltage high level 2.4 v low level 0.8 ton input voltage high level 2.4 v
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12.0.v, on3 = on5 = v cc , v shdn = 5v, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter conditions min typ max units clear fault level/smps off level 0.8 delay start level 1.7 2.3 on3, on5 input voltage smps on level 2.4 v v pro or v ton = 0 or 5v -1 +1 v on_ = 0 or 5v -1 +1 v skip = 0 or 5v -2 +2 v shdn = 0 or 24v -1 +1 v cs_ = 0 or 5v -2 +2 input leakage current v ilim3 , v ilim5 = 0 or 2v -0.2 +0.2 ? rising edge 1.2 2.0 shdn input trip level falling edge 0.96 1.04 v dh_ gate-driver on-resistance bst - lx_ forced to 5v 4.0 ? dl_, high state (pullup) 5.0 dl_ gate-driver on-resistance dl_, low state (pulldown) 1.5 ? out3, out5 discharge-mode on-resistance 40 ? out3, out5 discharge-mode synchronous rectifier turn-on level 0.2 0.4 v note 1: specifications to -40? are guaranteed by design, not production tested.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 8 _______________________________________________________________________________________ t ypical operating characteristics (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , shdn = v+, r cs = 7m ? , v ilim _ = 0.5v, t a = +25?, unless otherwise noted.) 100 0 0.001 0.01 0.1 1 10 max8732a 5v output efficiency vs. load current 20 max8732a/3a/4a toc01 load current (a) efficiency (%) 40 60 80 70 50 30 10 90 v in = 7v on5 = v cc on3 = gnd pfm mode pwm mode ultrasonic mode 100 0 0.001 0.01 0.1 1 10 max8732a 5v output efficiency vs. load current 20 max8732a/3a/4a toc02 load current (a) efficiency (%) 40 60 80 70 50 30 10 90 v in = 12v on5 = v cc on3 = gnd pfm mode pwm mode ultrasonic mode 100 0 0.001 0.01 0.1 1 10 max8732a 5v output efficiency vs. load current 20 max8732a/3a/4a toc03 load current (a) efficiency (%) 40 60 80 70 50 30 10 90 v in = 24v on5 = v cc on3 = gnd pfm mode pwm mode ultrasonic mode 100 0 0.001 0.01 0.1 1 10 max8733a 3.3v output efficiency vs. load current 20 max8732a/3a/4a toc04 load current (a) efficiency (%) 40 60 80 70 50 30 10 90 on5 = v cc on3 = v cc v in = 7v v in = 12v v in = 24v pfm mode pwm mode ultrasonic mode 1 10 100 0.1 7 10 13 16 19 22 25 max8732a no-load battery current vs. input voltage max8732a/3a/4a toc05 input voltage (v) battery current (ma) pwm mode ultrasonic mode pfm mode 1 10 100 0.1 7 10 13 16 19 22 25 max8733a no-load battery current vs. input voltage max8732a/3a/4a toc06 input voltage (v) battery current (ma) pwm mode ultrasonic mode pfm mode 170 176 174 172 180 178 188 186 184 182 190 7101316192225 standby input current vs. input voltage max8732a/3a/4a toc07 input voltage (v) standby input current ( a) max8732a max8733a 5.0 6.5 6.0 5.5 7.5 7.0 9.5 9.0 8.5 8.0 10.0 7101316192225 shutdown input current vs. input voltage max8732a/3a/4a toc08 input voltage (v) shutdown input current ( a) max8733a max8732a max8732a 5v output switching frequency vs. load current max8732a max8732a/3a/4a toc09 load current (a) switching frequency (khz) 1 0.1 0.01 25 50 75 100 125 150 175 200 225 250 0 0.001 10 v in = 7v pwm mode pfm mode ultrasonic mode idle mode is a trademark of maxim integrated products, inc.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , shdn = v+, r cs = 7m ? , v ilim _ = 0.5v, t a = +25?, unless otherwise noted.) 3.3v output switching frequency vs. load current (max8732a) max8732a/3a/4a toc10 load current (a) switching frequency (khz) 1 0.1 0.01 40 80 120 160 200 240 280 320 360 0 0.001 10 v in = 7v pwm mode pfm mode ultrasonic mode 250 0 0.001 0.01 0.1 1 10 max8732a 5v output switching frequency vs. load current 50 max8732a/3a/4a toc11 load current (a) switching frequency (khz) 100 150 200 175 125 75 25 225 pwm mode pfm mode v in = 24v ultrasonic mode 360 0 0.001 0.01 0.1 1 10 max8732a 3.3v output switching frequency vs. load current 80 max8732a/3a/4a toc12 load current (a) switching frequency (khz) 160 240 320 280 200 120 40 pwm mode pfm mode v in = 24v ultrasonic mode 450 0 0.001 0.01 0.1 1 10 max8733a 5v output switching frequency vs. load current 100 max8732a/3a/4a toc13 load current (a) switching frequency (khz) 200 300 400 350 250 150 50 v in = 7v pwm mode pfm mode ultrasonic mode 110 0 100 200 400 300 500 550 0.001 0.01 0.1 max8733a 3.3v output switching frequency vs. load current max8732a/3a/4a toc14 load current (a) switching frequency (khz) 450 350 250 150 50 pwm mode pfm mode v in = 7v ultrasonic mode 450 0 0.001 0.01 0.1 1 10 max8733a 5v output switching frequency vs. load current 100 max8732a/3a/4a toc15 load current (a) switching frequency (khz) 200 300 400 350 250 150 50 pwm mode pfm mode v in = 24v ultrasonic mode 110 0 100 200 400 300 500 550 0.001 0.01 0.1 max8733a 3.3v output switching frequency vs. load current max8732a/3a/4a toc16 load current (a) switching frequency (khz) 450 350 250 150 50 pwm mode pfm mode v in = 24v ultrasonic mode max8732a out5 voltage regulation vs. load current max8732a/3a/4a toc17 load current (a) output voltage (v) 1 0.1 0.01 5.07 5.09 5.11 5.13 5.15 5.17 5.19 5.05 0.001 10 ultrasonic idle mode forced-pwm max8732a out3 voltage regulation vs. load current max8732a/3a/4a toc18 load current (a) output voltage (v) 1 0.1 0.01 3.34 3.35 3.36 3.37 3.38 3.39 3.41 3.40 3.33 0.001 10 ultrasonic idle mode forced-pwm
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 10 ______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , shdn = v+, r cs = 7m ? , v ilim _ = 0.5v, t a = +25?, unless otherwise noted.) 4.95 4.96 4.97 4.98 4.99 5.00 0203040 10 50 60 70 90 80 100 ldo5 regulator output voltage vs. output current max8732a/3a/4a toc19 ldo5 output current (ma) ldo5 output voltage (v) 3.330 3.334 3.332 3.338 3.336 3.342 3.340 3.344 3.348 3.346 3.350 0203040 10 50 60 70 90 80 100 ldo3 regulator output voltage vs. output current max8732a/3a/4a toc20 ldo3 output current (ma) ldo3 output voltage (v) 1.995 1.997 1.996 2.000 1.999 1.998 2.001 2.002 2.004 2.003 2.005 -10 10 20 030405 060708090100 reference voltage vs. output current max8732a/3a/4a toc21 i ref ( a) v ref (v) 0 0 0 10v ref, ldo3, and ldo5 power-up max8732a/3a/4a toc22 400 s/div v+ 10v/div ldo5 2v/div ldo3 2v/div ref 1v/div 0 0 0 0 5v delayed-start waveforms (on3 = ref) max8732a/3a/4a toc23 100 s/div on5 5v/div out5 2v/div out3 2v/div 0 0 0 5v delayed-start waveforms (on5 = ref) max8732a/3a/4a toc24 100 s/div on3 5v/div out5 2v/div out3 2v/div 0 5a 0 3.3v 0 5a soft-start waveforms max8732a/3a/4a toc25 200 s/div i l5 5a/div out3 5v/div out5 5v/div i l3 5a/div 0 5v 0 3.3v 0 5v 0 5v shutdown waveforms max8732a/3a/4a toc26 10ms/div on3 5v/div out5 5v/div dl3 5v/div out3 5v/div 0 5v switching 0 4a 1a 5v max8732a/max8734a (ton = v cc ) 5v pwm-mode load transient response max8732a/3a/4a toc27 20 s/div v out , ac- coupled 100mv/div inductor current 2a/div dl5 5v/div 5v
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 11 0 4a 1a 5v max8733a/max8734a (ton = gnd) 5v pwm-mode load transient response max8732a/3a/4a toc28 10 s/div v out , ac- coupled 100mv/div inductor current 2a/div dl5 5v/div 5v 0 4a 1a 3.3v max8732a/max8734a (ton = v cc ) 3.3v pwm-mode load transient response max8732a/3a/4a toc29 20 s/div v out , ac- coupled 100mv/div inductor current 2a/div dl3 5v/div 5v 0 4a 1a 3.3v max8733a/max8734a (ton = gnd) 3.3v pwm-mode load transient response max8732a/3a/4a toc30 10 s/div v out , ac- coupled 100mv/div inductor current 2a/div dl3 5v/div 5v max8733a 5v output efficiency vs. load current max8732a/3a/4a toc31 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 on5 = v cc on3 = gnd v in = 7v v in = 12v v in = 24v pfm mode pwm mode ultrasonic mode max8733a 3.3v output efficiency vs. load current max8732a/3a/4a toc32 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 on5 = v cc on3 = v cc v in = 7v v in = 12v v in = 24v pfm mode pwm mode ultrasonic mode t ypical operating characteristics (continued) (circuit of figure 1 and figure 2, no load on ldo5, ldo3, out3, out5, and ref, v+ = 12v, on3 = on5 = v cc , shdn = v+, r cs = 7m ? , v ilim _ = 0.5v, t a = +25?, unless otherwise noted.)
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 12 ______________________________________________________________________________________ pin description pin max8732a max8733a max8734a name function 1 cs3 3.3v smps current-sense input. connect cs3 to a current-sensing resistor from the source of the synchronous rectifier to gnd. the voltage at ilim3 determines the current-limit threshold (see the current-limit circuit (ilim_) section). ? n.c. no connection. not internally connected. 22 pgood power-good output. pgood is an open-drain output that is pulled low if either output is disabled or is more than 10% below its nominal value. 33 on3 3.3v smps enable input. the 3.3v smps is enabled if on3 is greater than the smps on level and disabled if on3 is less than the smps off level. if on3 is connected to ref, the 3.3v smps starts after the 5v smps reaches regulation (delay start). drive on3 below the clear fault level to reset the fault latches. 44 on5 5v smps enable input. the 5v smps is enabled if on5 is greater than the smps on level and disabled if on5 is less than the smps off level. if on5 is connected to ref, the 5v smps starts after the 3.3v smps reaches regulation (delay start). drive on5 below the clear fault level to reset the fault latches. 55 ilim3 3.3v smps current-limit adjustment. the gnd-lx current-limit threshold defaults to 100mv if ilim3 is connected to v cc . in adjustable mode, the current-limit threshold is 1/10 the voltage seen at ilim3 over a 0.5v to 3v range. the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. connect ilim3 to ref for a fixed 200mv threshold. 66 shdn shutdown control input. the device enters its 6? supply current shutdown mode if v shdn is less than the shdn input falling-edge trip level and does not restart until v shdn is greater than the shdn input rising-edge trip level. connect shdn to v+ for automatic startup. shdn can be connected to v+ through a resistive voltage-divider to implement a programmable undervoltage lockout. 77 fb3 3.3v smps feedback input. connect fb3 to gnd for fixed 3.3v operation. connect fb3 to a resistive voltage-divider from out3 to gnd to adjust the output from 2v to 5.5v. 88 ref 2v reference output. bypass to gnd with a 0.22? (min) capacitor. ref can source up to 100? for external loads. loading ref degrades fb_ and output accuracy according to the ref load-regulation error. 99 fb5 5v smps feedback input. connect fb5 to gnd for fixed 5v operation. connect fb5 to a resistive voltage-divider from out5 to gnd to adjust the output from 2v to 5.5v. 10 10 pro overvoltage and undervoltage fault protection enable/disable. connect pro to v cc to disable undervoltage, overvoltage protection, and discharge mode (dl = low in shutdown). connect pro to gnd to enable undervoltage and overvoltage protection (see the fault protection section), and output discharge mode. 11 11 ilim5 5v smps current-limit adjustment. the gnd-lx current-limit threshold defaults to 100mv if ilim5 is connected to v cc . in adjustable mode, the current-limit threshold is 1/10 the voltage seen at ilim5 over a 0.5v to 3v range. the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. connect ilim5 to ref for a fixed 200mv threshold. 12 12 skip low-noise mode control. connect skip to gnd for normal idle-mode (pulse-skipping) operation or to v cc for pwm mode (fixed frequency). connect to ref or leave floating for ultrasonic mode (pulse skipping, 25khz min).
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 13 pin description (continued) pin max8732a max8733a max8734a name function 13 cs5 5v smps current-sense input. connect cs5 to a current-sensing resistor from the source of the synchronous rectifier to gnd. the voltage at ilim5 determines the current-limit threshold (see the current-limit circuit (ilim_) section). ?3 ton frequency select input. connect to v cc for 200khz/300khz operation and to gnd for 400khz/500khz operation (5v/3.3v smps switching frequencies, respectively). 14 14 bst5 boost flying capacitor connection for 5v smps. connect to an external capacitor and diode according to the typical application circuits (figure 1 and figure 2). see the mosfet gate drivers (dh_, dl_) section. 15 15 lx5 inductor connection for 5v smps. lx5 is the internal lower supply rail for the dh5 high-side gate driver. lx5 is the current-sense input for the 5v smps (max8734a only). 16 16 dh5 high-side mosfet floating gate-driver output for 5v smps. dh5 swings from lx5 to bst5. 17 17 v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage with a series 50 ? resistor. bypass to gnd with a 1? ceramic capacitor. 18 18 ldo5 5v linear-regulator output. ldo5 is the gate-driver supply for the external mosfets. ldo5 can provide a total of 100ma, including mosfet gate-drive requirements and external loads. the internal load depends on the choice of mosfet and switching frequency (see the reference and linear regulators (ref, ldo5, and ldo3) section). if out5 is greater than the ldo5 bootstrap switch threshold, the ldo5 regulator shuts down and the ldo5 pin connects to out5 through a 1.4 ? switch. bypass ldo5 with a minimum of 4.7?. use an additional 1? per 5ma of load. 19 19 dl5 5v smps synchronous rectifier gate-drive output. dl5 swings between gnd and ldo5. 20 20 v+ power-supply input. v+ powers the ldo5/ldo3 linear regulators and is also used for the quick-pwm on-time, one-shot circuits. connect v+ to the battery input and bypass with a 0.1? capacitor. 21 21 out5 5v smps output voltage-sense input. connect to the 5v smps output. out5 is an input to the quick-pwm on-time, one-shot circuit. it also serves as the 5v feedback input in fixed- voltage mode. if out5 is greater than the ldo5 bootstrap-switch threshold, the ldo5 linear regulator shuts down and ldo5 connects to out5 through a 1.4 ? switch. 22 22 out3 3.3v smps output voltage-sense input. connect to the 3.3v smps output. out3 is an input to the quick-pwm on-time, one-shot circuit. it also serves as the 3v feedback input in fixed- voltage mode. if out3 is greater than the ldo3 bootstrap-switch threshold, the ldo3 linear regulator shuts down and ldo3 connects to out3 through a 1.5 ? switch. 23 23 gnd analog and power ground 24 24 dl3 3.3v smps synchronous-rectifier gate-drive output. dl3 swings between gnd and ldo5. 25 25 ldo3 3.3v linear-regulator output. ldo3 powers up after ref is in regulation. ldo3 can provide a total of 100ma to external loads. if out3 is greater than the ldo3 bootstrap-switch threshold, the ldo3 regulator shuts down and the ldo3 pin connects to out3 through a 1.5 ? switch. bypass ldo3 with a minimum of 4.7?. use an additional 1? per 5ma of load. 26 26 dh3 high-side mosfet floating gate-driver output for 3.3v smps. dh3 swings from lx3 to bst3. 27 27 lx3 inductor connection for 3.3v smps. lx3 is the current-sense input for the 3.3v smps (max8734a only). 28 28 bst3 boost flying capacitor connection for 3.3v smps. connect to an external capacitor and diode according to the typical application circuits (figure 1 and figure 2). see the mosfet gate drivers (dh_, dl_) section.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 14 ______________________________________________________________________________________ t ypical application circuits the typical application circuits (figures 1 and 2) gener- ate the 5v/5a and 3.3v/5a main supplies in a notebook computer. the input supply range is 7v to 24v. table 1 lists component suppliers. detailed description the max8732a/max8733a/max8734a dual-buck, bicmos, switch-mode power-supply controllers gener- ate logic supply voltages for notebook computers. the max8732a/max8733a/max8734a are designed pri- marily for battery-powered applications where high effi- ciency and low-quiescent supply current are critical. the max8732a is optimized for highest efficiency with a 5v/200khz smps and a 3.3v/300khz smps, while the max8732a max8733a v in 7v to 24v 10 f 1/2 d1 0.1 f 0.1 f n1 fds6612a l5 5v c5 d3 ep10qy03 n2 irf7811av on off v cc ref 0.22 f 4.7 f 3.3v always on 1m ? 100k ? v cc 50 ? 1 f 5v always on 4.7 f 10 f 1 f 10 f 1/2 d1 vcc cmpsh-3a 0.1 f n3 fds6612a l3 3.3v c3 d2 ep10qy03 n4 irf7811av ldo5 ilim3 v cc v+ bst5 dh5 lx5 cs5 dl5 out5 fb5 pgood fb3 out3 dl3 lx3 dh3 bst3 ilim5 on5 on3 gnd shdn ref ldo3 pro skip 400khz/500khz max8733a 200khz/300khz max8732a 5v/3.3v smps switching frequency l3 l5 c3 c5 4.7 h 7.6 h 470 f 330 f 3.0 h 5.6 h 220 f 150 f frequency-dependent components 10 ? r cs 5 20m ? r cs 3 20m ? 10 ? cs3 figure 1. max8732a/max8733a typical application circuit manufacturer phone fax central semiconductor 516-435-1110 516-435-1824 dale-vishay 402-564-3131 402-563-6418 fairchild 408-721-2181 408-721-1635 international rectifier 310-322-3331 310-322-3332 niec (nihon) 805-843-7500 847-843-2798 sanyo 619-661-6835 619-661-1055 sprague 603-224-1961 603-224-1430 sumida 847-956-0666 847-956-0702 taiyo yuden 408-573-4150 408-573-4159 tdk 847-390-4461 847-390-4405 table 1. component suppliers
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 15 *optional capacitance between lx and pgnd (close to the ic) only required for ultrasonic mode max8734a v in 7v to 24v 10 f 1/2 d1 0.1 f 0.1 f n1 fds6612a l5 5v c5 d3 ep10qy03 n2 irf7811av on off v cc ref 0.22 f 4.7 f 3.3v always on 1m ? 100k ? v cc 50 ? 1 f 5v always on 4.7 f 10 f 1 f 10 f 1/2 d1 cmpsh-3a 0.1 f n3 fds6612a l3 3.3v c3 d2 ep10qy03 n4 irf7811av ldo5 ilim3 v cc vcc v+ bst5 dh5 lx5 dl5 out5 fb5 pgood fb3 out3 dl3 ton lx3 dh3 bst3 ilim5 on5 on3 gnd shdn ref ldo3 pro skip 400khz/500khz ton = gnd 200khz/300khz ton = v cc 5v/3.3v smps switching frequency l3 l5 c3 c5 4.7 h 7.6 h 470 f 330 f 3.0 h 5.6 h 220 f 150 f frequency-dependent components see table 10 ? 470pf* 10 ? 470pf* figure 2. max8734a typical application circuit
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 16 ______________________________________________________________________________________ max8733a is optimized for ?hin and light?applications with a 5v/400khz smps and a 3.3v/500khz smps. the max8734a provides a pin-selectable switching frequency, allowing either 200khz/300khz or 400khz/500khz operation of the 5v/3.3v smpss, respectively. light-load efficiency is enhanced by automatic idle- mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-charge losses. each step-down, the power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output fil- ter. the output voltage is the average ac voltage at the switching node, which is regulated by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel, high-side mosfet must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nf capacitor connected to bst_. max8732a max8733a max8734a ldo5 dl3 cs3 (max8732a/ max8733a) ilim3 fb3 out3 ldo3 on3 on5 shdn pro 2.91v 3v linear reg power-on sequence/ clear fault latch en3 thermal shutdown 5v linear reg 2v reference 3.3v smps pwm controller 5v smps pwm controller 4.56v pgood3 pgood5 pgood ldo5 bst5 dh5 lx5 en5 dl5 cs5 (max8732a/ max8733a) ilim5 fb5 out5 ldo5 v cc ref v+ gnd ton (max8734 only) bst3 dh3 lx3 figure 3. detailed functional diagram
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 17 each pwm controller consists of a dual-mode feedback network and multiplexer, a multi-input pwm comparator, high-side and low-side gate drivers, and logic. the max8732a/max8733a/max8734a contain fault-protection circuits that monitor the main pwm outputs for undervolt- age and overvoltage conditions. a power-on sequence block controls the power-up timing of the main pwms and monitors the outputs for undervoltage faults. the max8732a/max8733a/max8734a include 5v and 3.3v linear regulators. bias generator blocks include the 5v (ldo5) linear regulator, 2v precision reference, and auto- matic bootstrap switchover circuit. on-time compute t on t off trig trig one shot one shot q q q r s error amplifier current limit zero crossing q r s f ault latch 20ms blanking out ref ilim_ cs_ (max8732a/8733a) lx_ (max8734a) skip out_ fb_ 0.15v pro 0.9 x v ref 1.1 x v ref 0.7 x v ref ov_fault uv_fault pgood to dl_ driver to dh_ driver ton (max8734a) v+ figure 4. pwm controller (one side only)
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 18 ______________________________________________________________________________________ these internal blocks are not powered directly from the battery. instead, the 5v (ldo5) linear regulator steps down the battery voltage to supply both internal circuit- ry and the gate drivers. the synchronous-switch gate drivers are directly powered from ldo5, while the high- side switch gate drivers are indirectly powered from ldo5 through an external diode-capacitor boost cir- cuit. an automatic bootstrap circuit turns off the 5v lin- ear regulator and powers the device from out5 when out5 is above 4.56v. free-running, constant on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant on-time, current-mode type with voltage feed-forward. the quick-pwm control architec- ture relies on the output ripple voltage to provide the pwm ramp signal; thus, the output filter capacitor? esr acts as a current-feedback resistor. the high-side switch on-time is determined by a one-shot whose peri- od is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (300ns typ). the on-time, one-shot triggers when the following conditions are met: the error comparator is low, the synchronous rectifier current is below the current-limit threshold, and the minimum off- time one-shot has timed out. on-time, one-shot (t on ) each pwm core includes a one-shot that sets the high- side switch on-time for each controller. each fast, low- jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefit of a constant switching frequency is the frequency can be selected to avoid noise-sensitive frequency regions: see table 2 for approximate k-factors. the constant 0.075v is an approximation to account for the expected drop across the synchronous-rectifier switch. switching frequency increases as a function of load current due to the increasing drop across the synchronous rectifier, which causes a faster inductor-current discharge ramp. on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high-side power mosfet. also, the dead- time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode ( skip = v cc ) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor? emf causes lx to go high earlier than nor- mal, extending the on-time by a period equal to the dh- rising dead time. for loads above the critical conduction point, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the parasitic voltage drops in the charging path, including high-side switch, inductor, and pc board resistances, and t on is the on-time calculated by the max8732a/max8733a/max8734a. automatic pulse-skipping switchover (idle mode) in idle mode ( skip = gnd), an inherent automatic switchover to pfm takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- f vv tv v out drop on drop = + ++ () 1 2 t kv v v on out = + () + 0 075 . smps switching frequency (khz) k-factor (?) approximate k- factor error (%) max8732a/max8734a (t on = v cc ), 5v 200 5.0 ?0 max8732a/max8734a (t on = v cc ), 3.3v 300 3.3 ?0 max8733a/max8734a (t on = gnd), 5v 400 2.5 ?0 max8733a/max8734a (t on = gnd), 3.3v 500 2.0 ?0 table 2. approximate k-factor errors
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 19 tinuous and discontinuous inductor-current operation (also known as the critical conduction point): where k is the on-time scale factor (see the on-time one-shot (t on ) section). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 5). for example, in the max8732a typical application circuit with v out2 = 5v, v+ = 12v, l = 7.6?, and k = 5?, switchover to pulse-skipping operation occurs at i load = 0.96a or about 1/5 full load. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). dc output accuracy specifications refer to the trip level of the error comparator. when the inductor is in continuous conduction, the output voltage has a dc regulation higher than the trip level by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regulation higher than the trip level by approxi- mately 1.5% due to slope compensation. forced-pwm mode the low-noise, forced-pwm ( skip = v cc ) mode dis- ables the zero-crossing comparator, which controls the low-side switch on-time. disabling the zero-crossing detector causes the low-side, gate-drive waveform to become the complement of the high-side, gate-drive waveform. the inductor current reverses at light loads as the pwm loop strives to maintain a duty ratio of v out /v+. the benefit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10ma to 50ma, depending on switching frequency and the external mosfets. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback trans- former or coupled inductor. enhanced ultrasonic mode (25khz (min) pulse skipping) leaving skip unconnected or connecting skip to ref activates a unique pulse-skipping mode with a mini- mum switching frequency of 25khz. this ultrasonic pulse-skipping mode eliminates audio-frequency mod- ulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultra- sonic mode, the controller automatically transitions to fixed-frequency pwm operation when the load reaches the same critical conduction point (i load(skip) ) that occurs when normally pulse skipping. an ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 28?. once triggered, the ultrasonic controller pulls dl high, turning on the low-side mosfet to induce a negative inductor current. after the inductor current reaches the negative ultrasonic current threshold, the controller turns off the low-side mosfet (dl pulled low) and trig- gers a constant on-time (dh driven high). when the on- time has expired, the controller reenables the low-side mosfet until the controller detects that the inductor current dropped below the zero-crossing threshold. starting with a dl pulse greatly reduces the peak out- put voltage when compared to starting with a dh pulse. the output voltage at the beginning of the ultrasonic pulse determines the negative ultrasonic current thresh- old, resulting in the following equation: where v fb > v ref and r on is the on-resistance of the synchronous rectifier (max8734a) or the current-sense resistor value (max8732a/max8733a). virvv isonic l on ref fb ==? () 058 . i kv l vv v load skip out out () __ = +? + ? ? ? ? ? ? 2 inductor current i load = i peak / 2 on-time 0 time -i peak l v+ - v out ? i ? t = figure 5. pulse-skipping/discontinuous crossover point
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 20 ______________________________________________________________________________________ reference and linear regulators (ref, ldo5, and ldo3) the 2v reference (ref) is accurate to ?% over tem- perature, making ref useful as a precision system reference. bypass ref to gnd with a 0.22? (min) capacitor. ref can supply up to 100a for external loads. however, if extremely accurate specifications for both the main output voltages and ref are essential, avoid loading ref. loading ref reduces the ldo5, ldo3, out5, and out3 output voltages slightly because of the reference load-regulation error. two internal regulators produce 5v (ldo5) and 3.3v (ldo3). ldo5 provides gate drive for the external mosfets and powers the pwm controller, logic, refer- ence, and other blocks within the device. the ldo5 regulator supplies a total of 100ma for internal and external loads, including mosfet gate drive, which typically varies from 10ma to 50ma, depending on switching frequency and the external mosfets. ldo3 powers up when the reference (ref) is in regulation, and supplies up to 100ma for external loads. bypass ldo5 and ldo3 with a minimum 4.7? load; use an additional 1? per 5ma of internal and external load. when the 5v main output voltage is above the ldo5 bootstrap-switchover threshold, an internal 1.4 ? p-chan- nel mosfet switch connects out5 to ldo5 while simul- taneously shutting down the ldo5 linear regulator. similarly, when the 3.3v main output voltage is above the ldo3 bootstrap-switchover threshold, an internal 1.5 ? p-channel mosfet switch connects out3 to ldo3 while simultaneously shutting down the ldo3 linear regulator. these actions bootstrap the device, powering the internal circuitry and external loads from the output smps volt- ages, rather than through linear regulators from the bat- tery. bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing power from a 90%-efficient switch-mode source, rather than from a much-less-efficient linear regulator. current-limit circuit (ilim_) the current-limit circuit employs a ?alley?current-sens- ing algorithm. the max8734a uses the on-resistance of the synchronous rectifier, while the max8732a/ max8733a use a discrete resistor in series with the source of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at cs_ (max8732a/max8733a)/lx_ (max8734a) is above the current-limit threshold, the pwm is not allowed to initi- ate a new cycle (figure 7). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-limit threshold, inductor value, and input and output voltage. for the max8732a/max8733a, connect cs_ to the junction of the synchronous rectifier source and a cur- rent-sense resistor to gnd. with a current-limit threshold of 100mv, the accuracy is approximately ?%. using a lower current-sense threshold results in less accuracy. the current-sense resistor only dissipates power when the synchronous rectifier is on. for lower power dissipation, the max8734a uses the on-resistance of the synchronous rectifier as the cur- rent-sense element. use the worst-case maximum value for r ds(on) from the mosfet data sheet, and add some margin for the rise in r ds(on) with tempera- ture. a good general rule is to allow 0.5% additional resistance for each ? of temperature rise. the current limit varies with the on-resistance of the synchronous rectifier. the reward for this uncertainty is robust, loss- less overcurrent sensing. when combined with the on-time (t on ) zero-crossing detection i sonic 0 40 s (max) inductor current figure 6. ultrasonic current waveforms inductor current i limit i load 0 time -i peak figure 7. ?alley?current-limit threshold point
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 21 undervoltage-protection circuit, this current-limit method is effective in almost every circumstance. a negative current limit prevents excessive reverse inductor currents when v out sinks current. the nega- tive current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ilim_ is adjusted. the current-limit threshold is adjusted with an external voltage-divider at ilim_. the current-limit threshold adjustment range is from 50mv to 300mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage at ilim_. the threshold defaults to 100mv when ilim_ is connected to v cc . the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signals at cs_. mount or place the device close to the synchronous rectifier or sense resistor (whichever is used) with short, direct traces, making a kelvin-sense connection to the sense resistor. the cur- rent-sense accuracy of figure 8 is degraded if the schottky diode conducts during the synchronous recti- fier on-time. to ensure that all current passes through the sense resistor, connect the schottky diode in paral- lel with only the synchronous rectifier (figure 9) if the voltage drop across the synchronous rectifier and sense resistor exceeds the schottky diode? forward voltage. note that at high temperatures, the on-resis- tance of the synchronous rectifier increases and the forward voltage of the schottky diode decreases. mosfet gate drivers (dh_, dl_) the dh_ and dl_ gate drivers sink 2.0a and 3.3a, respectively, of gate drive, ensuring robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by diode-capacitor charge pumps at bst_. the dl_ synchronous-rectifier drivers are powered by ldo5. the internal pulldown transistors that drive dl_ low have a 0.6 ? typical on-resistance. these low on-resis- tance pulldown transistors prevent dl_ from being pulled up during the fast rise time of the inductor nodes due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfets. however, for high-current applications, some combinations of high- and low-side mosfets may cause excessive gate-drain coupling, which leads to poor efficiency and emi-producing shoot-through currents. adding a resis- tor in series with bst_ increases the turn-on time of the max8732a max8733a v+ dh_ dl_ cs_ lx_ out_ figure 8. current sensing using sense resistor (max8732a/max8733a) max8732a max8733a v+ dh_ dl_ cs_ lx_ out_ figure 9. more accurate current sensing with adjusted schottky connection max8732a max8733a max8734a 5v v in 10 ? bst dh lx figure 10. reducing the switching-node rise time
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 22 ______________________________________________________________________________________ high-side mosfets at the expense of efficiency, without degrading the turn-off time (figure 10). adaptive dead-time circuits monitor the dl_ and dh_ drivers and prevent either fet from turning on until the other is fully off. this algorithm allows operation without shoot-through with a wide range of mosfets, minimiz- ing delays and maintaining efficiency. there must be low-resistance, low-inductance paths from the gate dri- vers to the mosfet gates for the adaptive dead-time cir- cuit to work properly. otherwise, the sense circuitry interprets the mosfet gate as ?ff?when there is actual- ly charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the device). por, uvlo, and internal digital soft-start power-on reset (por) occurs when v+ rises above approximately 2.4v, resetting the undervoltage, over- voltage, and thermal-shutdown fault latches. ldo5 undervoltage-lockout (uvlo) circuitry inhibits switching when ldo5 is below 4v (typ). dl_ is low if pro is dis- abled; dl_ is high if pro is enabled. the output volt- ages begin to ramp up once v cc exceeds its 3.25v (typ) uvlo threshold and ref is in regulation. the internal digital soft-start timer begins to ramp up the maximum-allowed current limit during startup. the 1.7ms ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%. when ld05 falls below its 4v (typ) uvlo threshold, dh_ and dl_ are immediately forced low, and the out- puts are high impedance. ref is turned off when v cc falls below 3.25v (typ). dl_ is forced high again when v cc falls below its 1v (typ) por threshold. power-good output (pgood) the pgood comparator continuously monitors both out- put voltages for undervoltage conditions. pgood is actively held low in shutdown, standby, and soft-start. pgood releases and digital soft-start terminates when both outputs reach the error-comparator threshold. pgood goes low if either output turns off or is 10% below its nominal regulation point. pgood is a true open-drain output. note that pgood is independent of the state of pro . fault protection the max8732a/max8733a/max8734a provide over/undervoltage fault protection. drive pro low to activate fault protection. drive pro high to disable fault protection. once activated, the devices continuously monitor for both undervoltage and overvoltage conditions. overvoltage protection when the output voltage is 11% above the set voltage, the overvoltage fault protection activates. the synchro- nous rectifier turns on 100% and the high-side mosfet turns off. this rapidly discharges the output capacitors, decreasing the output voltage. the output voltage may dip below ground. for loads that cannot tolerate a neg- ative voltage, place a power schottky diode across the output to act as a reverse-polarity clamp. in practical applications, there is a fuse between the power source (battery) and the external high-side switches. if the overvoltage condition is caused by a short in the high- side switch, turning the synchronous rectifier on 100% creates an electrical short between the battery and gnd, blowing the fuse and disconnecting the battery from the output. once an overvoltage fault condition is set, it can only be reset by toggling shdn , on_, or cycling v+ (por). undervoltage protection when the output voltage is 30% below the set voltage for over 22ms (undervoltage shutdown blanking time), the undervoltage fault protection activates. both smpss stop switching. the two outputs start to discharge (see the discharge mode (soft-stop) section). when the output voltage drops to 0.3v, the synchronous rectifiers turn on, clamping the outputs to gnd. toggle shdn or on_, or cycle v+ (por) to clear the undervoltage fault latch. thermal protection the max8732a/max8733a/max8734a have thermal shutdown to protect the devices from overheating. thermal shutdown occurs when the die temperature exceeds +160?. all internal circuitry shuts down during thermal shutdown. the max8732a/max8733a/ max8734a may trigger thermal shutdown if ldo_ is not bootstrapped from out_ while applying a high input voltage on v+ and drawing the maximum current (including short circuit) from ldo_. even if ldo_ is boot- strapped from out_, overloading the ldo_ causes large power dissipation on the bootstrap switches, which may result in thermal shutdown. cycling shdn , on3, on5, or a v+ (por) ends the thermal-shutdown state. discharge mode (soft-stop) when pro is low and a transition to standby or shut- down mode occurs, or the output undervoltage fault latch is set, the outputs discharge to gnd through an internal 12 ? switch, until the output voltages decrease to 0.3v. the reference remains active to provide an accurate threshold and to provide overvoltage protec- tion. when both smps outputs discharge to 0.3v, the dl_ synchronous rectifier drivers are forced high. the
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 23 synchronous rectifier drivers clamp the smps outputs to gnd. when pro is high, the smps outputs do not discharge and the dl_ synchronous rectifier drivers remain low. shutdown mode drive shdn below the precise shdn input falling-edge trip level to place the max8732a/max8733a/max8734a in their low-power shutdown state. the max8732a/ max8733a/max8734a consume only 6a of quiescent current while in shutdown mode. when shutdown mode activates, the reference turns off, making the threshold to exit shutdown inaccurate. to guarantee startup, drive shdn above 2v ( shdn input rising-edge trip level). for automatic shutdown and startup, connect shdn to v+. if pro is low, both smps outputs are dis- charged to 0.3v through a 12 ? switch before entering true shutdown. the accurate 1v falling-edge threshold on shdn can be used to detect a specific analog volt- age level and shut down the device. once in shutdown, the 1.6v rising-edge threshold activates, providing suffi- cient hysteresis for most applications. for additional hysteresis, the undervoltage threshold can be made dependent on ref or ldo_, which go to 0v in shutdown. mode condition comment power-up ldo5 < uvlo threshold transitions to discharge mode after a v+ por and after ref becomes valid. ldo5, ldo3, and ref remain active. dl_ is active if pro is low. run shdn = high, on3 or on5 enabled normal operation. overvoltage protection either output > 111% of nominal level, pro = low dl_ is forced high. ldo3, ldo5 active. exited by a v+ por or by toggling shdn , on3, or on5. undervoltage protection either output < 70% of nominal after 22ms time- out expires and output is enabled, pro = low if pro is low, dl_ is forced high after discharge mode terminates. ldo3, ldo5 active. exited by a v+ por or by toggling shdn , on3, or on5. discharge pro is low and either smps output is still high in either standby mode or shutdown mode discharge switch (12 ? ) connects out_ to pgnd. one output may still run while the other is in discharge mode. activates when ldo_ is in uvlo, or transition to uvlo, standby, or shutdown has begun. ldo3, ldo5 active. standby on5, on3 < startup threshold, shdn = high dl_ stays high if pro is low. ldo3, ldo5 active. shutdown shdn = low all circuitry off. thermal shutdown t j > +160? all circuitry off. exited by v+ por or cycling shdn , on3, or on5. table 3. operating-mode truth table shdn ( v) v on3 ( v) v on5 ( v) ldo5 ldo3 5v smps 3v smps low x x off off off off ? 2.4?=> high low low on on (after ref powers up) off off ? 2.4?=> high high high on on (after ref powers up) on on ? 2.4?=> high high low on on (after ref powers up) off on ? 2.4?=> high low high on on (after ref powers up) on off ? 2.4?=> high high ref on on (after ref powers up) on (after 3v smps is up) on ? 2.4?=> high ref high on on (after ref powers up) on on (after 5v smps is up) table 4. power-up sequencing
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 24 ______________________________________________________________________________________ power-up sequencing and on/off controls (on3, on5) on3 and on5 control smps power-up sequencing. on3 or on5 rising above 2.4v enables the respective outputs. on3 or on5 falling below 1.6v disables the respective outputs. connecting on3 or on5 to ref forces the respective outputs off while the other output is below regulation and starts after that output regulates. the second smps remains on until the first smps turns off, the device shuts down, a fault occurs, or ldo5 goes into undervoltage lockout. both supplies begin their power-down sequence immediately when the first supply turns off. driving on_ below 0.8v clears the overvoltage, undervoltage, and thermal fault latches. adjustable-output feedback (dual-mode fb) connect fb_ to gnd to enable the fixed, preset smps output voltages (3.3v and 5v). connect a resistive volt- age-divider at fb_ between out_ and gnd to adjust the respective output voltage between 2v and 5.5v (figure 11). choose r2 to be approximately 10k ?, and solve for r1 using the equation: where v fb = 2v nominal. when using the adjustable-output mode, set the 3.3v smps lower than the 5v smps. ldo5 connects to out5 through an internal switch only when out5 is above the ldo5 bootstrap-switch threshold (4.56v). ldo3 con- nects to out3 through an internal switch only when out3 is above the ldo3 bootstrap switch threshold (2.91v). bootstrapping is most effective when the fixed output voltages are used. once ldo_ is bootstrapped from out_, the internal linear regulator turns off. this reduces internal power dissipation and improves effi- ciency when ldo_ is powered with a high input voltage. design procedure establish the input voltage range and maximum load current before choosing an inductor and its associated ripple-current ratio (lir). the following four factors dic- tate the rest of the design: 1) input voltage range. the maximum value (v+ (max) ) must accommodate the maximum ac adapter volt- age. the minimum value (v+ (min) ) must account for the lowest input voltage after drops due to connec- tors, fuses, and battery selector switches. lower input voltages result in better efficiency. 2) maximum load current. the peak load current (i load(max) ) determines the instantaneous compo- nent stress and filtering requirements, and thus dri- ves output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stress and drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. 3) switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage and mosfet switching losses. the max8732a has a nominal switching frequency of 200khz for the 5v smps and 300khz for the 3.3v smps. the max8733a has a nominal switching fre- quency of 400khz for the 5v smps and 500khz for the 3.3v smps. the max8734a has a pin-selec- table switching frequency. 4) inductor ripple current ratio (lir). lir is the ratio of the peak-to-peak ripple current to the aver- age inductor current. size and efficiency trade-offs must be considered when setting the inductor rip- ple current ratio. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the cir- cuit to operate at critical conduction (where the inductor current just touches zero with every cycle rr v v out fb 12 1 = ? ? ? ? ? ? ? ? ? _ max8732a max8733a max8734a dh_ dl_ gnd out_ fb_ v+ r1 r2 v out_ figure 11. setting v out_ with a resistor-divider
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 25 at maximum load).inductor values lower than this grant no further size-reduction benefit. the max8732a/max8733a/max8734as?pulse-skip- ping algorithm (skip = gnd) initiates skip mode at the critical conduction point, so the inductor? operating point also determines the load current at which pwm/pfm switchover occurs. the optimum point is usually found between 20% and 50% ripple current. inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 5a, v+ = 12v, v out5 = 5v, f = 200khz, 35% ripple current or lir = 0.35: find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice. the core must be large enough not to saturate at the peak inductor current (i peak ): i peak = i load(max) + [(lir / 2) x i load(max) ] the inductor ripple current also impacts transient- response performance, especially at low v+ - v out_ differences. low inductor values allow the inductor cur- rent to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the peak amplitude of the output transient (v sag ) is also a function of the maximum duty factor, which can be cal- culated from the on-time and minimum off-time: where minimum off-time = 0.350? (max) and k is from table 2. determining the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: i limit(low) > i load(max) - [(lir / 2) x i load(max) ] where i limit(low) = minimum current-limit threshold voltage divided by the r ds(on) of n2/n4 (max8734a). for the max8732a/max8733a/max8734a, the mini- mum current-limit threshold voltage is 93mv (ilim_ = v cc ). use the worst-case maximum value for r ds(on) from the mosfet n2/n4 data sheet and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each ? of temperature rise. examining the 5a circuit example with a maximum r ds(on) = 12m ? at high temperature reveals the following: i limit(low) = 93mv / 12m ? > 5a - (0.35 / 2) 5a 7.75a > 4.125a 7.75a is greater than the valley current of 4.125a, so the circuit can easily deliver the full-rated 5a using the fixed 100mv nominal current-limit threshold voltage. connect the source of the synchronous rectifier to a current-sense resistor to gnd (max8732a/max8733a), and connect cs_ to that junction to set the current limit for the device. the max8732a/max8733a/max8734a limit the current with the sense resistor instead of the r ds(on) of n2/n4. the maximum value of the sense resistor can be calculated with the equation: i lim_ = 93mv / r sense output-capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capaci- tance must also be high enough to absorb the inductor energy while transitioning from full-load to no-load con- ditions without tripping the overvoltage fault latch. in applications where the output is subject to large load transients, the output capacitor? size depends on how much esr is needed to prevent the output from dip- ping too low under a load transient. ignoring the sag due to finite capacitance: where v dip is the maximum-tolerable transient voltage drop. in non-cpu applications, the output capacitor? size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: r v i esr dip load max () v ilk v v t cvk vv v t sag load max out off min out out out off min = ? () + + ? ? ? ? ? ? ? ? +? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () _ () _ _ () 2 2 l vv v v khz a h = ? () = 512 5 12 200 0 35 5 83 . . l vvv vf lir i out_ out_ load(max) = +? () +
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 26 ______________________________________________________________________________________ where v p-p is the peak-to-peak output voltage ripple. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lum, os-con, and other electrolytic-type capacitors). when using low-capacity filter capacitors such as polymer types, capacitor size is usually determined by the capacity required to prevent v sag and v soar from tripping the undervoltage and overvoltage fault latches during load transients in ultrasonic mode. for low input-to-output voltage differentials (v in / v out < 2), additional output capacitance is required to main- tain stability and good efficiency in ultrasonic mode. the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. stability considerations stability is determined by the value of the esr zero (f esr ) relative to the switching frequency (f). the point of instability is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. low-esr capacitors (especially polymer or tantalum), in widespread use at the time of publication, typically have esr zero frequencies lower than 30khz. in the design example used for inductor selection, the esr needed to support a specified ripple voltage is found by the equation: where lir is the inductor ripple current ratio and i load is the average dc load. using lir = 0.35 and an aver- age load current of 5a, the esr needed to support 50mv p-p ripple is 28m ? . do not place high-value ceramic capacitors directly across the fast-feedback inputs (out_ to gnd for inter- nal feedback, fb_ divider point for external feedback) without taking precautions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. adding a discrete resistor or placing the capacitors a couple of inches downstream from the junction of the inductor and out_ may improve stability. unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feed- back loop instability. noise on the output or insufficient esr may cause double pulsing. insufficient esr does not allow the amplitude of the voltage ramp in the output signal to be large enough. the error comparator mistak- enly triggers a new cycle immediately after the 350ns minimum off-time period has expired. double pulsing results in increased output ripple, and can indicate the presence of loop instability caused by insufficient esr. loop instability results in oscillations or ringing at the output after line or load perturbations, causing the out- put voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the max8734a ev kit data sheet) and observe the output voltage-ripple envelope for overshoot and ringing. monitoring the inductor current with an ac current probe can also provide some insight. do not allow more than one cycle of ringing of under- or overshoot after the initial step response. input-capacitor selection the input capacitors must meet the input-ripple-current (i rms ) requirement imposed by the switching current. the max8732a/max8733a/max8734a dual switching regulators operate at different frequencies. this inter- leaves the current pulses drawn by the two switches and reduces the overlap time where they add together. the input rms current is much smaller in comparison than with both smpss operating in phase. the input rms cur- rent varies with load and the input voltage. esr v lir i ripple p p load () = ? f rc esr esr out = 1 2 f f esr v il cv soar peak out out = 2 2 _ r v lir i esr pp load max ? ()
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 27 the maximum input capacitor rms current for a single smps is given by: when v+ = 2 x v out_ (d = 50%), i rms has a maximum current of i load / 2. the esr of the input capacitor is important for deter- mining capacitor power dissipation. all the power (i rms 2 x esr) heats up the capacitor and reduces effi- ciency. nontantalum chemistries (ceramic or os-con) are preferred due to their low esr and resilience to power-up surge currents. choose input capacitors that exhibit less than +10? temperature rise at the rms input current for optimal circuit longevity. place the drains of the high-side switches close to each other to share common input bypass capacitors. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (> 5a) when using high-voltage (> 20v) ac adapters. low-current applications usually require less attention. choose a high-side mosfet (n1/n3) that has conduc- tion losses equal to the switching losses at the typical battery voltage for maximum efficiency. ensure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. ensure that conduction losses plus switching losses at the maximum input voltage do not exceed the package ratings or violate the overall ther- mal budget. choose a synchronous rectifier (n2/n4) with the lowest possible r ds(on) . ensure the gate is not pulled up by the high-side switch turning on due to parasitic drain-to-gate capacitance, causing crossconduction problems. switching losses are not an issue for the synchronous rectifier in the buck topology since it is a zero-voltage switched device when using the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty-factor extremes. for the high-side mosfet, the worst-case power dissipation (pd) due to the mosfet? r ds(on) occurs at the minimum battery voltage: generally, a small high-side mosfet reduces switch- ing losses at high input voltage. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mosfet can be. the opti- mum situation occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. switching losses in the high-side mosfet can become an insidious heat problem when maximum battery volt- age is applied, due to the squared term in the cv 2 ? f switching-loss equation. reconsider the high-side mosfet chosen for adequate r ds(on) at low battery voltages if it becomes extraordinarily hot when subject- ed to v+ (max) . calculating the power dissipation in n h (n1/n3) due to switching losses is difficult since it must allow for quan- tifying factors that influence the turn-on and turn-off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source induc- tance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for bench eval- uation, preferably including verification using a thermo- couple mounted on n h (n1/n3): where c oss is the output capacitance of n h (n1/n3), q g(sw) is the switch gate charge of n h , and i gate is the peak gate-drive source/sink current. for the synchronous rectifier, the worst-case power dis- sipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, ?verdesign?the circuit to tolerate: i load = i limit(high) + (lir / 2 ) x i load(max) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and resistance variation. pd n v v ir l out in max load ds on () =? ? ? ? ? ? ? 1 2 _ () () pd n switching cv f viqf i h oss in max sw in max load g sw sw gate () () () () () = + 2 2 pd n sis ce v v ir h out in min load ds on (re tan ) _ () () = ? ? ? ? ? ? ? ? () 2 ii vvv v rms load out out +? () + ? ? ? ? ? ? ? ? ? ? __
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 28 ______________________________________________________________________________________ rectifier selection current circulates from ground to the junction of both mosfets and the inductor when the high-side switch is off. as a consequence, the polarity of the switching node is negative with respect to ground. this voltage is approximately -0.7v (a diode drop) at both transition edges while both switches are off (dead time). the drop is i l x r ds(on) when the low-side switch conducts. the rectifier is a clamp across the synchronous rectifier that catches the negative inductor swing during the dead time between turning the high-side mosfet off and the synchronous rectifier on. the mosfets incorporate a high-speed silicon body diode as an adequate clamp diode if efficiency is not of primary importance. place a schottky diode in parallel with the body diode to reduce the forward-voltage drop and prevent the n2/n4 mosfet body diodes from turning on during the dead time. typically, the external diode improves the efficiency by 1% to 2%. use a schottky diode with a dc current rating equal to 1/3 of the load current. for example, use an mbr0530 (500ma-rated) type for loads up to 1.5a, a 1n5819 type for loads up to 3a, or a 1n5822 type for loads up to 10a. the rectifier? rated reverse-breakdown voltage must be at least equal to the maximum input volt- age, preferably with a 20% derating factor. boost supply diode a signal diode, such as a 1n4148, works well in most applications. use a small (20ma) schottky diode for slightly improved efficiency and dropout characteris- tics, if the input voltage can go below 6v. do not use large power diodes, such as 1n5817 or 1n4001, since high-junction capacitance can force ldo5 to excessive voltages. applications information dropout performance the output voltage-adjust range for continuous-conduc- tion operation is restricted by the nonadjustable 350ns (max) minimum off-time, one-shot. use the slower 5v smps for the higher of the two output voltages for best dropout performance in adjustable feedback mode. the duty-factor limit must be calculated using worst-case val- ues for on- and off-times, when working with low input voltages. manufacturing tolerances and internal propaga- tion delays introduce an error to the t on k-factor. also, keep in mind that transient-response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the output-capacitor selection section). the absolute point of dropout occurs when the inductor current ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down indicates the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow tradeoffs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on- time, one-shot section), t off(min) is from the ec table, and k is taken from table 2. the absolute minimum input voltage is calculated with h = 1. operating frequency must be reduced or h must be increased and output capacitance added to obtain an acceptable v sag if calculated v+ (min) is greater than the required minimum input voltage. calculate v sag to be sure of adequate transient response if operation near dropout is anticipated. dropout design example max8733a: with v out5 = 5v, fsw = 400khz, k = 2.25?, t off(min) = 350ns, v drop1 = v drop2 = 100mv, and h = 1.5, v vv th k vv min out drop off min drop drop += + () ? ? ? ? ? ? ? ? ? +? () _ () 1 21 1 max8732a max8733a max8734a v+ 12v positive secondary output 5v main output dl_ dh_ t1 10 h 1:2.2 t1 = transpower technologies tti-5870 max1658/ max1659 ldo figure 12. transformer-coupled secondary output
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 29 the minimum v+ is: calculating with h = 1 yields: therefore, v+ must be greater than 6.65v. a practical input voltage with reasonable output capacitance would be 7.5v. use of coupled inductors to create auxiliary outputs a coupled inductor or transformer can be substituted for the inductor in the 5v or 3.3v smps to create an auxiliary output (figure 12). the max8732a/max8733a/ max8734a are particularly well suited for such applica- tions because they can be configured in ultrasonic or forced-pwm mode to ensure good load regulation when the main supplies are lightly loaded. an additional postregulation circuit can be used to improve load regula- tion and limit output current. the power requirements of the auxiliary supply must be considered in the design of the main output. the trans- former must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. the power ratings of the synchronous-rectifier mosfets and the current limit in the max8732a/max8733a/max8734a must also be adjusted accordingly. extremes of low input-output dif- ferentials, widely different output loading levels, and high turns ratios can further complicate the design due to par- asitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage induc- tance. power from the main and secondary outputs is combined to get an equivalent current referred to the main output. use this total current to determine the cur- rent limit (see the determining the current limit section): where i total is the equivalent output current referred to the main output and p total is the sum of the output power from both the main output and the secondary output: where l primary is the primary inductance, n is the transformer turns ratio, v sec is the minimum-required rectified secondary voltage, v fwd is the forward drop across the secondary rectifier, v out(min) is the minimum value of the main output voltage, and v rect is the on- state voltage drop across the synchronous rectifier mosfet. the transformer secondary return is often con- nected to the main output voltage instead of ground to reduce the necessary turns ratio. in this case, subtract v out from the secondary voltage (v sec - v out ) in the transformer turns-ratio equation above. the secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60v, which usually rules out most schottky rectifiers. common sili- con rectifiers, such as the 1n4001, are also prohibited because they are too slow. this often makes fast silicon rectifiers such as the murs120 the only choice. the fly- back voltage across the rectifier is related to the v in - v out difference, according to the transformer turns ratio: v flyback = v sec + (v in - v out ) ? n where n is the transformer turns ratio (secondary wind- ings/primary windings), v sec is the maximum secondary dc output voltage, and v out is the primary (main) out- put voltage. if the secondary winding is returned to v out instead of ground, subtract v out from v flyback in the equation above. the diode? reverse breakdown voltage rating must also accommodate any ringing due to leak- age inductance. the diode? current rating should be at least twice the dc load current on the secondary output. the optional linear postregulator must be selected to deliver the required load current from the transformer? rectified dc output. the linear regulator should be con- figured to run close to dropout to minimize power dissi- pation and should have good output accuracy under those conditions. input and output capacitors are cho- sen to meet line regulation, stability, and transient requirements. there is a wide variety of linear regulators appropriate for this application; consult the specific lin- ear-regulator data sheet for details. widely different output loads affect load regulation. in particular, when the secondary output is left unloaded while the main output is fully loaded, the secondary out- put capacitor may become overcharged by the leakage inductance, reaching voltages much higher than intend- ed. in this case, a minimum load or overvoltage protec- l vv v vi lir n vv vv primary out in max out in max total sec fwd out min rect = ? ? = + + ( () () () ipv total total out = / v vv s s vv v min += + () ? ? ? ? ? ? ? ? +?= () . . . .. . 501 1 035 1 225 01 01 604 v vv s s vv v min += + () ? ? ? ? ? ? ? ? +?= () . .. . .. . 501 1 035 15 225 01 01 665
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 30 ______________________________________________________________________________________ tion may be required on the secondary output to protect any device connected to this output. pc board layout guidelines careful pc board layout is critical to achieve minimal switching losses and clean, stable operation. this is especially true when multiple converters are on the same pc board where one circuit can affect the other. the switching power stages require particular attention (figure 13). refer to the max1999 ev kit i.c. data sheet for a specific layout example. mount all of the power components on the top side of the board with their ground terminals flush against one another, if possible. follow these guidelines for good pc board layout: isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the out3 and out5 sides (called pgnd3 and pgnd5). avoid the introduction of ac currents into the pgnd3 and pgnd5 ground planes. run the power plane ground currents on the top side only, if possible. use a star ground connection on the power plane to minimize the crosstalk between out3 and out5. keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable effi- ciency penalty. cs_ (max8732a/max8733a)/lx_ (max8734a) and gnd connections to the synchronous rectifiers for current limiting must be made using kelvin-sense connections to guarantee the current-limit accuracy. with 8-pin so mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connecting cs_/lx_ traces inside (underneath) the mosfets. when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the syn- chronous rectifier or between the inductor and the output filter capacitor. ensure that the out_ connection to c out_ is short and direct. however, in some cases it may be desirable to deliberately introduce some trace length between the out_ connector node and the output filter capacitor (see the stability considerations section). route high-speed switching nodes (bst_, dh_, lx_, and dl_) away from sensitive analog areas (ref, ilim_, and fb_). use pgnd3 and pgnd5 as an emi shield to keep radiated switching noise away from the ic? feedback divider and analog bypass capacitors. agnd pgnd via to out5 ground out3 out5 via to out3 via to pgnd via to lx5 v+ via to lx3 use agnd plane to: - bypass v cc and ref - terminate external fb divider (if used) - terminate r ilim (if used) - pin-strap control inputs use pgnd plane to: - bypass ldo_ - connect pgnd to the topside star ground vias to ground note: example shown is for dual i.c. n-channel mosfet. analog ground plane on inner layer c4 c3 c1 n4 d1 d2 n2 c2 l1 l2 connect pgnd to agnd beneath the controller at one point only as shown. via between power and analog ground n3 n1 figure 13. pc board layout example
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers ______________________________________________________________________________________ 31 make all pin-strap control input connections ( skip , ilim_, etc.) to gnd or v cc of the device. layout procedure 1) place the power components first with ground ter- minals adjacent (n2/n4 source, c in_ , c out_ , d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the synchronous- rectifier mosfets, preferably on the back side to keep dh_, gnd, and the dl_ gate drive lines short and wide. the dl_ gate trace must be short and wide, measuring 50 mils to 100 mils wide if the mosfet is 1in from the controller device. 3) group the gate-drive components (bst_ diode and capacitor, v+ bypass capacitor) together near the controller device. 4) make the dc-dc controller ground connections as follows: near the device, create a small analog ground plane. connect the small analog ground plane to gnd (figure 13) and use the plane for the ground connection for the ref and v cc bypass capacitors, fb dividers, and ilim resistors (if any). create another small ground island for pgnd, and use the plane for the v+ bypass capacitor, placed very close to the device. connect the agnd and pgnd planes together at the gnd pin of the device. 5) on the board? top side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors and synchronous rectifiers. keep the resistance low between the star ground and the source of the synchronous rectifiers for accurate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). create pgnd islands on the layer just below the top-side layer (refer to the max1999 ev kit for an example) to act as an emi shield if multiple layers are available (highly recommended). connect each of these individually to the star ground via, which connects the top side to the pgnd plane. add one more solid ground plane under the device to act as an additional shield, and also connect the solid ground plane to the star ground via. 6) connect the output power planes (v core and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. table 5. max8732a/max8733a/max8734a and max1777/max1977/max1999 differences max8732a/max8733a/max8734a max1777/max1977/max1999 line transient behavior improved line transient behavior requires only a 0.1? filter capacitor on v+. allows fast rising-edge line transients of 10v/? and falling-edge line transients of 5v/?. a 4 ? /4.7? filter capacitor is required on v+ to limit the dv/dt on the v+ pin. ultrasonic mode simplified z pattern offers better efficiency and smoother transition into continuous- conduction mode. original ??pattern conducts through the high- side mosfet? body diode, reducing efficiency. transition between ultrasonic mode and continuous-conduction mode is not as smooth. ldo3 and ldo5 sequencing ldo3 starts only after ldo5 is in regulation, reducing the inrush current when shdn goes high. ldo3 and ldo5 start up together at the current limit of each ldo, causing large inrush currents through the 4 ? series resistor at v+. soft-shutdown enable delay soft-shutdown (10 ? discharge feature) is enabled immediately when an output is enabled, and is not dependent on the 22ms ( typ) startup undervoltage blanking timer. soft-shutdown (10 ? discharge feature) is enabled only after the 22ms (typ) startup undervoltage blanking time. this causes dl_ to be driven high if the part is commanded to turn off before the 22ms timer. high-output impedance in uvlo when ldo5 falls below its 4v (typ) uvlo threshold, dh_ and dl_ are immediately pulled low, and the outputs are high impedance. the outputs are discharged by the load. when ldo5 falls below its 4v (typ) uvlo threshold, dh_ is immediately pulled low and dl_ forced high to clamp the output rails. this causes the outputs to swing below ground.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers 32 ______________________________________________________________________________________ ordering information (continued) part temp range pin- pa cka ge 5v/3v switching frequency ( khz) max8734a eei+ -40? to +85? 28 qsop 200/300 or 400/500 max8734aeei -40? to +85? 28 qsop 400khz/500 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bst3 lx3 dh3 ldo3 dl3 gnd lx5 out3 out5 v+ dl5 ldo5 v cc dh5 bst5 cs5 ilim5 fb5 ref fb3 ilim3 on5 on3 pgood cs3 qsop top view max8732a max8733a shdn pro skip pin configurations (continued) chip information transistor count: 8335 process: bicmos +denotes lead free package.
max8732a/max8733a/max8734a high-efficiency, quad-output, main power- supply controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max8734a part number table notes: see the max8734a quickview data sheet for further information on this product family or download the max8734a full data sheet (pdf, 1.1mb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max8734aeei+g104 -40c to +85c rohs/lead-free: yes max8734aeei+t qsop;28 pin;.150" dwg: 21-0055f (pdf) use pkgcode/variation: e28+1 * -40c to +85c rohs/lead-free: yes materials analysis max8734aeei+ qsop;28 pin;.150" dwg: 21-0055f (pdf) use pkgcode/variation: e28+1 * -40c to +85c rohs/lead-free: yes materials analysis max8734aeei qsop;28 pin;.150" dwg: 21-0055f (pdf) use pkgcode/variation: e28-1 * -40c to +85c rohs/lead-free: no materials analysis max8734aeei-t qsop;28 pin;.150" dwg: 21-0055f (pdf) use pkgcode/variation: e28-1 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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